In computer and information processing systems, various integrated circuit chips must communicate digitally with each other over common buses. The receiving bus nodes recognize the signal as being high or low using receivers, also referred to as input buffers. Often the receiver is a differential receiver, i.e., a receiver that detects the difference between two input signals, referred to as the differential inputs. These input signals may be a received signal and a reference voltage or they may be a received signal and the inverse of the received signal. In either case, it is the difference between the two input signals that the receiver detects in order to determine the state of the received signal.
Integrated circuits are powered at certain voltage levels, which levels are then provided to the various components, such as the receivers, which are located on the integrated circuit. However, the nominal supply voltage for integrated circuits keeps being decreased to reduce power consumption. Additionally, fluctuations of the voltage level during operation can make the voltage level powering a receiver even lower. The lower the supply voltage, the more challenging it is to get a receiver to operate reliably.
The signal frequency at which communication occurs can limit the performance of the overall system. Thus, the higher the communication frequency, the better. The maximum frequency at which a system communicates is a function not only of the time that it takes for the electromagnetic wavefronts to propagate on the bus from one chip to another, but also of the time required for the signals to be reliably recognized at the receiving bus nodes as being high or low. Characteristics that affect the time in which a signal is recognized by a receiver include the set up time of the receiver, i.e., the amount of time before a clock edge that a signal must arrive and settle to a recognized level, and the hold time of the receiver, i.e., the time that the received signal must stay at a certain level in order for that level to be detected by the receiver. Other characteristics that affect the ability of the receiver to determine that state of the received signal include the ability of the receiver to reject input noise and power supply noise and sensitivity, i.e., the ability of the receiver to resolve small voltage differences between the differential inputs of the receiver. There are many kinds of receivers, inverters, differential amplifiers, and sense amplifiers. Sense type of receivers have the advantage of good sensitivity, i.e., almost zero setup time and a specific hold time. These features improve timing for high speed I/O interfaces.
Referring to FIG. 1, a sense amp type input receiver generally includes a differential sense amplifier (10) having a single-ended inverter chain (9). The differential sense amplifier (10) compares the received input voltage (PAD) with the reference voltage (Vref) and resolves the small difference between them using cross-coupled inverters having cross-coupled pmos transistors (101) and (102) and cross-coupled nmos transistors (103) and (104). This cross-coupled inverters are disabled during the pre-charge phase using the transistor (105) and outputs (Sense) and ({overscore (Sense)}) are pre-charged to VDD using transistors (116) and (120) and equalization is done using transistor (118). During the evaluate phase, voltage difference between the PAD and Vref results in differential voltage across the cross-coupled inverters by enabling transistor (105), (which is enabled by eval_clk) and transistors (106) and (110) (which are enabled by dclk). Cross-coupled inverters amplifies even the small voltage difference between the PAD and Vref because of the positive feed back mechanism. A full swing (0 to VDD, or vice-versa) is realized on the (Sense) and ({overscore (Sense)}) lines.
The lines (Sense) and ({overscore (Sense)}) lines are then fed to the output stage, i.e., the single-ended inverter chain (9). The output (Sense) is fed to inverter (1) and output of which is fed to inverter (2). The output ({overscore (Sense)}) is fed to inverter(3). The output of inverter (2) is fed to gate of pmos transistor (4) and output of inverter (3) fed to gate of nmos transistor (5). Transistors (4) and (5) are connected a latch having of inverters (6) and (7) and output inverter (8). The pair of transistors (4) and (5) are connected in series between VDD and Ground (GND) and coupled through inverter (8) to the output (Q). This latch is updated with the (Sense) and ({overscore (Sense)}) lines during the evaluate phase. (Sense) and ({overscore (Sense)}) always resolve to the same logic at the output ({overscore (Q)}) because (Sense) passes through three inverting stages, (1), (2), and (4) and ({overscore (Sense)}) passes through two inverting stages (3) and (5). In this implementation, differential nature of (Sense) and ({overscore (Sense)}) is not used which results in increased delay from (eval_clk) to Q.
In one or more embodiments, a sense amplifier type input receiver comprises a differential receiver circuit operatively coupled to an output stage. The output stage comprises a pass gate enabled latch. The differential receiver circuit may output a first differential output and a second differential output. The output stage may comprise a first pass gate operatively coupled between the first differential output and an output of the output stage, a second pass gate operatively coupled between the second differential output and the pass gate enabled latch, and the pass gate enabled latch may be operatively coupled to the output of the output stage. A clock signal may be coupled to the first pass gate to enable passing of the first differential output to the output of the output stage, the clock signal may be coupled to the second pass gate to enable passing of the second differential output to the pass gate enabled latch, and the clock signal coupled to a pass gate of the pass gate enabled latch to enable operation of the pass gate enabled latch. A second clock signal may be coupled to the first pass gate to enable passing of the first differential output to the output of the output stage, the second clock signal may be coupled to the second pass gate to enable passing of the second differential output to the pass gate enabled latch, and the clock second signal coupled to a pass gate of the pass gate enabled latch to enable operation of the pass gate enabled latch. A first inverter may be operatively coupled between the first differential output and the first pass gate, a second inverter operatively coupled between the second differential output and the second pass gate, and a third inverter operatively coupled to the output of the output stage.
In one or more embodiments, a method of conditioning the output of a differential receiver circuit comprises operatively coupling a differential receiver circuit to an output stage. The output stage comprises a pass gate enabled latch. The differential receiver circuit may output a first differential output and a second differential output and the method may further comprise operatively coupling a first pass gate in the output stage between the first differential output and an output of the output stage, operatively coupling a second pass gate in the output stage between the second differential output and the pass gate enabled latch, and operatively coupling the pass gate enabled latch is to the output of the output stage. The method may further comprise coupling a clock signal to the first pass gate to enable passing of the first differential output to the output of the output stage, coupling the clock signal to the second pass gate to enable passing of the second differential output to the pass gate enabled latch, and coupling the clock signal to a pass gate of the pass gate enabled latch to enable operation of the pass gate enabled latch. The method may further comprise coupling a second clock signal to the first pass gate to enable passing of the first differential output to the output of the output stage, coupling the second clock signal to the second pass gate to enable passing of the second differential output to the pass gate enabled latch, and coupling the second clock signal to a pass gate of the pass gate enabled latch to enable operation of the pass gate enabled latch. The method may further comprise operatively coupling a first inverter between the first differential output and the first pass gate, operatively coupling a second inverter between the second differential output and the second pass gate, and operatively coupling a third inverter to the output of the output stage.
In one or more embodiments, a sense amplifier type input receiver comprises a differential receiver circuit operatively coupled to output means.
Other advantages and features will become apparent from the following description, including the figures and the claims.